The present invention is generally related to the fabrication of integrated circuits (ICs) and, more specifically, to the fabrication of a three-dimensional, one transistor/one capacitor (1T/1C), ferroelectric structure.
Platinum (Pt) and other noble metals are used in IC ferroelectric capacitors. The use of noble metals is motivated by their inherent chemical resistance. This property is especially desirable under high temperature oxygen annealing conditions, such as those seen in the fabrication of ferroelectric capacitors. In addition, chemical interaction between noble metals and ferroelectric materials, such as perovskite metal oxides, is negligible.
The above-mentioned noble metals are used as conductive electrode pairs separated by a ferroelectric material. One, or both of the electrodes are often connected to transistor electrodes, or to electrically conductive traces in the IC. As is well known, these ferroelectric devices can be polarized in accordance with the voltage applied to the electrode, with the relationship between charge and voltage expressed in a hysteresis loop. When used in memory devices, the polarized ferroelectric device can be used to represent a xe2x80x9c1xe2x80x9d or a xe2x80x9c0xe2x80x9d. These memory devices are often called ferro-RAM, or FeRAM. Ferroelectric devices are nonvolatile. That is, the device remains polarized even after power is removed from the IC in which the ferroelectric is imbedded.
There are problems in the use of noble metal electrodes. Platinum (Pt), iridium (Ir), palladium (Pd), rhodium (Rh), and the other noble metals are notoriously difficult to remove by standard etching techniques. Therefore, it is difficult to form noble metal electrodes through conventional metal deposition techniques that rely on selective etching to form the electrode areas. As a result, extra process steps must be added to the fabrication process to electrically connect a transistor electrode to a noble metal ferroelectric capacitor electrode.
In co-pending patent application Ser. No. 09/247,655, entitled xe2x80x9cChemically Active Slurry for the Patterning of Noble Metals and Method for Samexe2x80x9d, invented by David R. Evans, filed on Mar. 3, 1999, a method is described for removing a noble metal film using a CMP process. The above-mentioned co-pending patent application is incorporated herein by reference.
It would be advantageous if a ferroelectric electrode could be fabricated using a noble metal without the complicated process steps needed to etch and form a noble metal electrode.
It would be advantageous if a noble metal electrode could be fabricated directly adjoining a transistor electrode without the need of an electrical interconnection structure. It would be advantageous to minimize the resistance between the bottom electrode of a ferroelectric capacitor and a transistor electrode.
It would be advantageous if the capacitance associated with a ferroelectric capacitor could be increased without complicated process steps, and increasing the cell area.
Accordingly, a ferroelectric device has been provided comprising a transistor including a source, and a ferroelectric capacitor. The ferroelectric capacitor includes a bottom electrode layer, including a noble metal, directly overlying and in contact with the transistor source. A ferroelectric film overlies the bottom electrode layer and a top electrode layer overlies the ferroelectric film. In this manner, a noble metal electrode is formed without any intervening structures between the source and the bottom electrode.
A IC insulator, having a top surface, is deposited over the transistor, and a via, with via sidewalls, is formed between the IC insulator top surface and the source. The bottom electrode is formed to overlie the via sidewalls, as well as the source. A ferroelectric film is formed over the bottom electrode, and a top electrode is formed over the ferroelectric film. In this manner, a three-dimensional capacitor structure is formed in the via from consecutive linings of the top electrode over the ferroelectric, over the bottom electrode. Therefore, the diameter of the via includes at least two thickness of bottom electrode, two thicknesses of ferroelectric material, and at least one thickness of top electrode.
Alternately, a dual damascene structure is formed in the IC insulator which includes a first trench in addition to the first via. Then, the bottom electrode, ferroelectric film, and the top electrode are layered to overlie the via and trench bottoms and sidewalls so that the volume of the ferroelectric capacitor can be increased. The trench can be formed over the transistor gate electrode to conserve space.
In another alternative, an electrical interconnection is formed to the drain, simultaneous with the formation of the ferroelectric capacitor. Then, a via is formed, extending from the IC insulator top surface to the drain. The bottom electrode material is formed over the exposed drain areas and the drain via sidewalls. The bottom electrode material provides an interconnect between the drain and an overlying metal level. Typically, a ferroelectric film is formed over the bottom electrode material in the drain via. The drain via has a diameter that is no larger than the minimum size contact hole size of the associated IC technology, plus the two thicknesses of bottom electrode lining the via.
A method of forming the above-mentioned ferroelectric device is also provided. The method comprises the steps of:
a) forming a transistor; and
b) forming a ferroelectric capacitor bottom electrode, including a noble metal, immediately overlying the source of the transistor. The ferroelectric capacitor is formed without an intervening electrical connector between the source and bottom electrode. Additional steps precede Step b), of:
a1) forming an IC insulator layer with a top surface overlying the source; and
a2) forming a via opening, with a via bottom and via sidewalls, extending from the IC insulator layer top surface to selected area of the transistor first electrode, whereby a damascene ferroelectric capacitor structure is formed. Step b) includes forming the bottom electrode over the bottom of the via and the via sidewalls. Further steps, follow Step b), of:
c) forming a ferroelectric film over the bottom electrode; and
d) forming a top electrode layer over the ferroelectric film, whereby the via bottom and sidewalls are lined with the top electrode over the ferroelectric film, over the bottom electrode.
Step b) includes isotropically depositing a noble metal material overlying the IC insulator top surface, via sidewalls, and source. Then, the bottom electrode material, overlying the IC insulator top surface, is removed. The removal process entails: a) depositing nitride over the IC insulator top surface and source; b) chemical mechanically polishing (CMP) to remove the nitride and bottom electrode material over the IC insulator top surface; and c) etching to remove the nitride, not removed in the previous step, in the via over the source, whereby the bottom electrode material is left overlying the first via sidewalls and the source. Nitride is particularly useful when the IC insulator material is an oxide because of the etch selectivity between the two materials.
After conformal deposition of the ferroelectric film in Step c), and conformal deposition of the top electrode material in Step d), Step e) etches the top electrode material overlying the first IC insulator top surface. Typically, the ferroelectric film over the IC insulator top surface is removed in the same process.
An interconnection is formed to the transistor drain simultaneous with the formation of the ferroelectric capacitor. Step a2) includes forming a second via extending from the IC insulator layer top surface to the drain. Step b) forms a bottom electrode layer over the drain and drain via sidewalls. Typically, Step c) forms a ferroelectric film over the bottom electrode layer, but it is not required.
Alternately, Step a2) includes forming a dual damascene opening in the first IC insulator including the via and a trench, with via and trench bottoms, and via and trench sidewalls. Step b) includes forming the ferroelectric capacitor bottom electrode overlying the transistor first electrode in the dual damascene opening. Specifically, Step b) includes isotropically depositing the bottom electrode material overlying the first via and first trench bottom and sidewalls, Step c) includes isotropically depositing the ferroelectric film material over the bottom electrode, and Step d) includes isotropically depositing the top electrode layer overlying the ferroelectric.